Electronics devices and capabilities have grown extremely common in daily life. Along with personal computers in the home, many individuals carry more than one productivity tool for various and sundry purposes. Most personal productivity electronic devices include some form of non-volatile memory. Cell phones utilize non-volatile memory in order to store and retain user programmed phone numbers and configurations when the power is turned off. Personal Computer Memory Card International Association (xe2x80x9cPCMCIAxe2x80x9d) cards utilize non-volatile memory to store and retain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in un-powered assemblies.
Non-volatile memory manufacturers that sell to the electronic equipment manufacturers require testers to exercise and verify the proper operation of the memories that they produce. Due to the volume of non-volatile memories that are manufactured and sold at consistently low prices, it is very important to minimize the time it takes to test a single part. Purchasers of non-volatile memories require memory manufacturers to provide high shipment yields because of the cost savings associated with the practice of incorporating the memory devices into more expensive assemblies with minimal or no testing. Accordingly, the memory testing process must be sufficiently efficient to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single test process.
As non-volatile memories become larger, denser and more complex, the testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. As memories evolve and improve, the tester must be able to easily accommodate the changes made to the device. Another issue specific to testing non-volatile memories is that repeated writes to cells of the memories can degrade the overall lifetime performance of the part. Non-volatile memory manufacturers have responded to many of the testing issues by building special test modes into the memory devices. These test modes are not used at all by the purchaser of the memory, but may be accessed by the manufacturer to test all or significant portions of the memories in as little time as possible and as efficiently as possible. Some non-volatile memories are also capable of being repaired during the test process. The tester, therefore, should be able to identify: a need for repair; a location of the repair; the type of repair needed; and, must then be able to perform the appropriate repair. Such a repair process requires a tester that is able to detect and isolate a specific nonconforming portion of the memory. In order to take full advantage of the special test modes as well as the repair functions, it is beneficial for a tester to be able to execute a test program that supports conditional branching based upon an expected response from the device.
From a conceptual perspective, the process of testing memories is an algorithmic process. As an example, typical tests include sequentially incrementing or decrementing memory addresses while writing 0""s and 1""s into the memory cells. It is customary to refer to a collection of 1""s and 0""s being written or read during a memory cycle as a xe2x80x9cvectorxe2x80x9d, while the term xe2x80x9cpatternxe2x80x9d refers to a sequence of vectors. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking 1""s and butterfly patterns. A test developer can more easily and efficiently generate a program to create these patterns with the aid of algorithmic constructs. A test pattern that is algorithmically coherent is also easier to debug and use logical methods to isolate portions of the pattern that do not perform as expected. A test pattern that is generated algorithmically using instructions and commands that are repeated in programming loops consume less space in tester memory. Accordingly, it is desirable to have algorithmic test pattern generation capability in a memory tester.
Precise signal edge placement and detection is also a consideration in the effectiveness of a non-volatile tester. In order to capture parts that are generally conforming at a median while not conforming within the specified margins, a non-volatile memory tester must be able to precisely place each signal edge relative in time to another signal edge. It is also important to be able to precisely measure at which point in time a signal edge is received. Accordingly, a non-volatile memory tester should have sufficient flexibility and control of the timing and placement of stimuli and responses from the Device Under Test (xe2x80x9cDUTxe2x80x9d), here a memory.
Memory testers are said to generate transmit vectors that are applied (stimulus) to the DUT, and receive vectors that are expected in return (response). The algorithmic logic that generates these vectors can generally do so without troubling itself about how a particular bit in a vector is to get to or from a particular signal pad in the DUT. At this level it is almost as if it were a certainty that adjacent bits in the vector would end up as physically adjacent signals on the DUT. Life should be so kind!
In reality, the correspondence between bits in a vector at the xe2x80x9cconceptual levelxe2x80x9d and the actual signals in the DUT is apt to be rather arbitrary. If nothing were done to prevent it, it might be necessary to cross one or more probe wires as they descend from a periphery to make contact with the DUT. Such crossing is most undesirable, and it is convention to incorporate a mapping mechanism in the path of the transmit vector to rearrange the bit positions in the transmit vector before they are applied to the DUT, so that task of making physical contact is not burdened with crossings. Receive vectors are correspondingly applied to a reverse mapping mechanism before being considered. In this way the algorithmic vector generation and comparison mechanisms can be allowed to ignore this entire issue. As another example of what such mappers and reverse mappers can do, consider the case when a different instance of the same type of DUT is laid out on the same wafer, but with a rotation or some mirrored symmetry, in order to avoid wasting space on the wafer. These practices also have an effect on the correspondence between vector bit position and physical signal location, but which can be concealed by the appropriate mappings and reverse mappings. It will be appreciated that the mappings and reverse mappings needed for these situations are, once identified for a particular DUT, static, and need not change during the course of testing for that particular DUT.
Historically, application specific integrated circuits (ASICs) are used in memory testers in order to take advantage of the efficiency associated with an ASIC designed to perform a few complex tasks many times. In order to properly test larger memories the tester must be equipped with a significant amount of memory to properly store all of the test vectors that comprise a single test program. The tester must also be faster than the memory it is testing in order to properly characterize and test the timing characteristics of the integrated circuit (xe2x80x9cICxe2x80x9d). Historically, memory testers use static random access memory (xe2x80x9cSRAMxe2x80x9d) for program storage. The SRAM is embedded into the tester ASIC to achieve the greatest tester efficiency. SRAM is useful because it exhibits a minimum latency permitting accurate reproduction of timing conditions for testing purposes. SRAM, however, is costly. As test programs increase in size, a natural solution is to merely increase the amount of embedded SRAM in order to accommodate the entire test program. SRAM, however, is expensive. It is difficult to cost-effectively embed a sufficient amount of SRAY, into the tester ASIC to accommodate storage of all test patterns used in some useful test programs. An alternative to a large embedded SRAM is a large and cost effective memory that is located external of the sequencer, specifically a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). Disadvantageously, there is a significant read latency associated with DRAM. This read latency would render any testing of timing characteristics indeterminable and therefore unusable.
There is a need, therefore, for a method and apparatus of using the benefit of the minimum latency SRAM as well as the benefit of the cost effective DRAM to achieve the desired result of an IC tester capable of executing a lengthy test program without being limited by the latency inherent in DRAM.
A method for executing an IC test program, the IC test program comprising main program instructions, at least one called subroutine, and at least one subroutine calling instruction, the method comprising the steps of partitioning the subroutine into first and second subroutine portions, loading the main program instructions into a primary memory, the main program instructions including at least one of said calling instructions, loading the first portion at a location in the primary memory contiguous with the calling instruction, inserting a memory transfer access instruction after the first portion, and loading a remainder of the main program instructions into the primary memory. The method continues with the steps of fetching and executing instructions from the primary memory, executing the calling instruction from the primary memory, the calling instruction causing the second portion of the called subroutine to be loaded into a tertiary memory from a secondary memory, executing the first portion from the-primary memory, and executing the memory transfer access instruction to initiate the steps of fetching and executing the second portion of the called subroutine from the tertiary memory. The method further comprises the steps of executing a return instruction in the second portion of the called subroutine, and the resumes fetching and executing the main program instructions from the primary memory.
An apparatus for executing an IC test program routine comprises a primary memory having main program instructions and at least one first portion of a called subroutine stored therein, a secondary memory having program instructions of subroutines called in the main program instructions stored therein, and a tertiary memory comprising a FIFO element connected to the secondary memory. The apparatus also comprises a memory controller capable of directing access and storage of the subroutine instructions located in the secondary memory from the secondary memory to the tertiary memory upon execution of a secondary memory access instruction in the program instructions located in the primary memory, and a sequencer connected to the primary and tertiary memories, wherein the sequencer accesses and executes the program instructions stored in the primary and tertiary memories as directed by the program instructions.
A method for compiling an IC test program source code into object code wherein the source code is a test pattern having a calling instruction and having a called subroutine comprises the steps of partitioning the called subroutine into a first portion and a second portion and converting the first portion into first portion object code and converting the second portion into second portion object code. The method continues with the steps of evaluating the test pattern including the calling instruction, converting each line of source code of the test pattern into corresponding object code, inserting a copy of the first portion object code into the object code test pattern contiguous with the calling instruction, inserting a secondary memory access instruction into the test pattern after and contiguous with the first portion object code in said test pattern, and converting each remaining line of source code of the test pattern into corresponding object code. The method for compiling then stores the resulting test pattern object code into a test pattern file for downloading into a primary memory, and stores the second portion object code into a subroutine file for downloading into secondary memory.
Advantageously, a method and apparatus used in a memory tester according to the teachings of the present invention permits efficient and cost effective use of DRAM in conjunction with SRAM to achieve lengthy test patterns without affecting the timing of the test program execution.